1. Field of the Invention
The present invention is directed to a method for the manufacture of LSI, complementary MOS field effect transistor circuits wherein p-doped or n-doped wells are generated in the semiconductor substrate for the formation of n-channel or p-channel transistors. The required dopants are introduced into the wells by ion implantations in order to set the various transistor threshold voltages. An n.sup.+ -doped or p.sup.+ -doped silicon having an n.sup.- -doped or p.sup.- -doped epitaxial layer situation on the substrate is employed as the semiconductor substrate. The manufacture of the source/drain and gate regions as well as the generation of intermediate and insulating oxides plus formation of the interconnect levels are performed in accordance with the known method steps of MOS technology.
2. Description of the Prior Art
An overall method for producing LSI complementary MOS field effect transistor circuits may be found, in general, in European Patent Application No. 0 135 163.
Modern CMOS processes employ technologies wherein both the n- as well as p-channel transistors occur in wells. Setting the various transistor threshold voltages of thin oxide transistors and field oxide transistors of both types is accomplished by multiple ion implantations. An increased latch-up hardness, i.e., suppression of the parasitic bipolar effects was previously obtained either by employing an epitaxial layer on a low impedance substrate or by employing a "retrograde well".
The use of an epitaxial layer in a CMOS process is disclosed in an article by L.C. Parillo et al. in Technical Digest IEDM 1980, 29.1, pages 752 through 755. The two n-doped or p-doped wells are produced in a CMOS process by means of self-adjusting process steps through the use of a mask. The self-adjusting implantation of the two wells leads to a substantial local overlap and charge compensation of the n-implanted or p-implanted regions at the implantation edge using the standard depth of 5 microns of the n-well or p-well. The effect thereof is that the threshold voltage of the field oxide transistor is reduced and the current gain of the parasitic npn and pnp bipolar transistors is increased, thus leading to increase latch-up susceptibility.
Another method which uses an epitaxial layer for increasing the latch-up hardness is described in European Patent Application No. 0 135 163. In this method, the threshold voltages of the n-channel and p-channel CMOS field effect transistors are set by specific gate materials and adjusted by gate oxide thicknesses as well as by a specific channel implantation.
Both described methods have the disadvantage that the sheet resistance of the p-well is in the region of a number of kilo-ohms per square, thus reducing the latch-up susceptibility but not making it impossible. Moreover, the sensitivity of the MOS FET located in the well relative to substrate currents is relatively high.
The employment of a "retrograde well" in a CMOS process is known from an article by R.D. Rung et al. in IEEE Transactions on Electron Devices, vol. ED-28, no 10, October 1981, pages 1115 through 1119. In this method, a p- or n-well profile having an increasing doping in the depth is produced by employing a deep implantation with a short diffusion step following. A shallower well is produced not affecting the sheet resistance and reducing the n.sup.+ /p.sup.+ spacing to about one-third its former value. A disadvantage of this method is in the necessity of adding expensive technology in the form of high energy implantation.